This application claims the priority benefit of Taiwan application serial no. 87112531, filed Jul. 30, 1998, the full disclosure of which is incorporated herein by reference.
1. Field of Invention
The present invention relates to a method of manufacturing a dynamic random access memory (DRAM) capacitor. More particularly, the present invention relates to a method that utilizes a porous oxide layer in the process of forming a DRAM capacitor.
2. Description of Related Art
At present, ultra-large scale integration (ULSI) semiconductor fabrication techniques have considerably increased circuit density on a silicon chip. However, to achieve high circuit density, the dimensions of each device must be downsized correspondingly and devices must be packed closer together. Since the structure of DRAM is suitable for high-density packing, DRAMs are extensively used in the electronic industry for data storage. Each DRAM comprises a large number of memory cells, and data is stored according to the charging state in the capacitor of a memory cell. The data is accessed through memory peripheral address and read/write circuits around the silicon chip. Furthermore, each DRAM cell includes a field effect transistor (FET) and a capacitor so that a single bit of information is represented by each cell. The capacitor of a DRAM cell is a critical element of the unit. The larger the amount of electric charges that can be stored in a DRAM capacitor, the smaller the effect of noise on the read out data is. For example, soft errors due to a - particles can be greatly reduced.
As the number of transistors on a DRAM chip continues to increase, the size of each transistor must be reduced. Consequently, the amount of charges within each DRAM capacitor must be small enough to produce an acceptable signal-to-noise level. However, if the amount of charges stored in a capacitor is further lowered, the number of refresh cycles has to be increased. Therefore, in order to provide a larger capacitance without having to occupy a greater surface area on a silicon chip, more efficient capacitor structures are required.
In general, trench-type and stacked-type capacitors are the two most commonly used capacitor structures. Among the two, trench-type capacitors are less frequently used because they are more difficult to fabricate. A stacked capacitor has a structure that extends vertically up from a substrate surface, and hence is capable of providing greater capacitor area without having to deal with too many manufacturing problems. There are a number of variations in the design of a stacked capacitor. FIG. 1 is a cross-sectional view of a conventional, cylindrical-type, stacked capacitor, and FIG. 2 is a cross-sectional view of a conventional, fin-type stacked capacitor. Both cylindrical and fin-type capacitors are capable of increasing surface area of the capacitor so that more electric charges can be stored.
The cylindrical-shaped capacitor shown in FIG. 1 is built upon a semiconductor substrate 10. The capacitor has a source/drain region 12 in the substrate 10 and an insulating layer 14 above the substrate 10. Within the insulating layer 14, there is a storage node opening 15. Furthermore, there is a cylindrical-shaped capacitor structure 19 in and on top of the storage node opening 15. The cylindrical-shaped capacitor structure 19 further includes a lower electrode 16, a dielectric layer 17 and an upper electrode 18.
The fin-shaped capacitor as shown in FIG. 2 is built upon a semiconductor substrate 20. The capacitor has a source/drain region 22 in the substrate 20 and an insulating layer 24 above the substrate 20. Within the insulating layer 24, there is a storage node opening 25. Furthermore, there is a fin-shaped capacitor structure 29 in and on top of the storage node opening 25. The fin-shaped capacitor structure 29 further includes a lower electrode 26, a dielectric layer 27 and an upper electrode 28.
Although the above stacked capacitors can increase the surface area of a capacitor somewhat, larger surface area and more efficient methods of fabrication are always in demand to bring down the cost.
In light of the foregoing, there is still a need to improve the method of manufacturing DRAM capacitor.
Accordingly, the present invention provides a method that employs plasma-etching techniques in combination with a porous oxide layer mask for manufacturing a DRAM capacitor whose lower electrode has a larger surface area.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a DRAM capacitor. The method includes the steps of providing a semiconductor substrate having a source/drain region thereon, and then forming an insulating layer over the substrate. Next, a storage node opening that exposes the source/drain region is formed in the insulating layer, and then a first conductive layer is formed above the storage node opening and the insulating layer. Thereafter, porous insulating material is deposited over the first conductive layer. The porous material includes porous oxide, sold under the trademark NanoPorous Silicon(trademark) or a Xerogel Sol-Gel# for example. Subsequently, the porous oxide layer is used as a mask for carrying out a plasma-etching operation so that a portion of the first conductive layer is etched away. Therefore, a multiple of long and narrow crevices is etched out forming a fork-shaped first conductive layer structure. The fork-shaped first conductive layer serves as the lower electrode of a capacitor. Subsequently, the porous oxide layer is removed, and then a dielectric layer is formed over the fork-shaped structure. Finally, a second conductive layer that serves as the upper electrode of a capacitor is formed over the dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.